1. Field of the Invention
The present invention relates to semiconductor packages and manufacturing methods thereof, and more specifically, to a leadframe-based semiconductor package with an increased number of electrical input/output (I/O) connections and a manufacturing method thereof.
2. Description of Prior Art
Conventional leadframe semiconductor package, such as a quad flat package (QFP), has a manufacturing method that requires a die pad and a leadframe with a plurality of leads. A semiconductor chip is mounted on a die pad with a plurality of bonding wires electrically connected to the bonding pads of the semiconductor chip and the corresponding plurality of leads. Moreover, a package encapsulant is used to encapsulate the semiconductor chip and the bonding wires to form a leadframe semiconductor package.
The disadvantage of the conventional leadframe semiconductor package is that leads used for electrical input/output pins can only be aligned on the four peripheral sides of the package body, and therefore the number of I/O connections that this structure can provide is limited by the size of the package body. In order to solve the aforementioned problem, the ball grid array semiconductor package was then invented.
Conventional ball grid array (BGA) semiconductor package involves a manufacturing method that uses a substrate with a plurality of trace patterns on top and bottom surfaces. A semiconductor chip is mounted on the top of the substrate and bonding wires are used to interconnect bonding pads of the semiconductor chip and ends of the trace pattern on the top side of the substrate. Then, through the routing circuits internal to the substrate and the vias, the trace pattern on the top of the substrate is electrically connected to the trace pattern on the bottom of the substrate. The goal is to mount a solder ball on a solder ball pad, which is terminated by ends of the trace pattern on the bottom of the substrate. The solder ball electrically connects the semiconductor chip to the external device. More I/O connections can be obtained by I/O assignment on the whole substrate surface.
The fabrication process of the trace pattern on the top substrate surface, the internal conductive structures of the substrate and the trace layout on the bottom substrate surface is complicated and of a high cost for such a ball grid array semiconductor package, therefore such package structure is only capable of providing high density of I/O connections but has the drawback of high cost. Consequently, it is unable to satisfy the requirements of low cost and high I/O density in the industry.
For further information, referring to FIG. 1, a semiconductor package that combines the ball-grid array substrate and the leads is disclosed in U.S. Pat. No. 5,854,512. This semiconductor package is capable of providing a higher density of I/O connections, as it mainly provides a substrate 11 with a first trace pattern 11 and a second trace pattern 112 laid on the respective top and bottom surfaces. In addition, the first trace pattern 111 on the surface of the substrate 11 is attached with a plurality of leads 12 of a leadframe by using a non-conductive adhesive. A semiconductor chip 13 is placed on the top surface of the substrate 11 thereby allowing the semiconductor chip 13 to be electrically connected to a bonding finger 1110 of the first trace pattern 111 and the leads 12 via bonding wires 14. Subsequently, form, on the substrate 11, a package encapsulant that encapsulates the semiconductor chip 13 and the bonding wires 14. On the substrate 11, the solder ball pad 1120 fixed on the second trace pattern 112 is mounted with the solder ball 16 and the leads 12 are bent, forming a ball-grid array semiconductor package that has leads. Additional I/O connection counts are provided via installation of the leads. Relevant technology content may be referred to U.S. Pat. Nos. 4,763,188 5,420,758 5,365,409 5,438,478 5,386,141 5,283,717 and 5,502,289.
However, the cost of the conventional ball-grid array (BGA) semiconductor package process is still too high and not accepted by the industry.
Referring to FIGS. 2A and 2E, U.S. Pat. No. 6,876,068 discloses an inexpensive BGA substrate structure to increase the electrical I/O connections on the leadframe semiconductor package and its manufacturing method. The leadframe semiconductor package provides a leadframe 22 which comprises a die pad 220, a plurality of first leads 221 attached to the internal peripheral of the die pad 220, and a plurality of second leads 222 attached, but spaced by a distance, to the external peripheral of the die pad 220, wherein the first leads 221 form a spaced open slot 2210 with a first supporting bar 2211 attached to the first leads, and the second leads 222 has a second supporting bar 2221 attached to it (as shown in FIGS. 2A and 2B, wherein FIG. 2B is a cross-sectional view of FIG. 2A); a semiconductor chip 23 is placed on the die pad 220 and the chip is electrically connected to the first leads 221 and the second leads 222 via a plurality of bonding wire 24 (as depicted in FIG. 2C). A package encapsulant 25 is formed to encapsulate the semiconductor chip 23, the die pad 220, the first leads 221 and partial second leads 222 to allow the bottom surface of the die pad 220, the bottom surface of the first leads 221 and the external part of the second leads 222 to be exposed outside of the package encapsulant 25 (as shown in FIG. 2D). Subsequently etching or cutting will be applied to the first supporting bar 2211 to separate the first leads 221 and separate the second leads 222; the second leads 222 is additionally bent. Installation of the first leads 221 will increase the number of usable electrical I/O connections on the package structure.
However, the aforementioned process requires etching or cutting to separate the first leads, the process is not only complicated but also costly. Also the etched or cut part of the first leads can be easily broken and attacked by moisture due to insufficient encapsulating of the package encapsulant. In addition, the cross-sectional surface of the etched or cut part of the first leads can be easily oxidized, thus when the surface mount technology (SMT) is used to solder the packaged component onto the external device in the future, wetting of the tin will be ineffective, leading to defected soldering. Besides, when the arrangement of the first leads is of a high density, package molding can easily cause the electrical connection contacts of the bottom surface of the first leads to be encapsulated by resin flash of the package encapsulant during the package molding process, thereby requiring an additional undesired encapsulant removal process.
Therefore, a way to provide a leadframe semiconductor package that is of a low cost and capable of providing a plurality of additional electrical I/O connections, and its manufacturing method as well as a package structure that can at the same time be exempted from a separation process by etching and cutting, thereby preventing occurrence of cracks, humidification, ineffective wetting, encapsulant flash in the additional electrical I/O connections is the immediate subject that concerns the relevant industry.